The present invention generally relates to a method for plating copper conductors on an electronic substrate and devices formed by the method and more particularly, relates to a method for plating copper conductors on an electronic substrate in a plating bath kept at a temperature below 18xc2x0 C. with a low dopant concentration resulting in improved resistance transient in plated copper films and devices made by such method.
In the recent development of semiconductor fabrication technologies, the replacement of aluminum-copper alloy by pure copper as a chip interconnection material results in numerous advantages in the chip performance. Conventionally, aluminum-copper and its related alloys have been used as a preferred metal conductor material for forming interconnections on electronic devices such as IC chips. The copper content in an aluminum-copper alloy is limited typically to a range between about 0.3 and about 4%.
The chip performance made possible by pure copper or copper alloys includes a lower electrical resistivity since the resistivity of copper and certain copper alloys is less than the resistivity of aluminum-copper. Based on the low resistivity of copper, narrower lines can be used and higher wiring densities can also be realized.
While the advantages of copper metalization have been recognized by many in the semiconductor industry, copper metalization has been the subject of extensive research effort in recent years. Semiconductor processes such as chemical vapor deposition (CVD) and electroless plating are popularly used for depositing copper. Both of these methods of deposition produce at best conformal deposits and sometimes lead to defects such as voids in a wiring structure, especially when trenches are deposited which have a cross-section narrower at the top than at the bottom as a result of an imperfect reactive ion etching process. Similarly, while the electroless plating technique offers the advantage of low cost, the evolution of hydrogen gas during deposition leads to blistering and other void defects which are detrimental to the quality and reliability of IC devices built.
One such electroplating processes for depositing copper, silver or gold onto a semiconductor wafer is described in U.S. Pat. No. 5,256,274 issued in 1993. In this patent, a copper conductor which is obtained with a seam at is center is judged as a good deposition while a copper conductor with a void at its center is judged as bad deposition. The plating bath utilized in the patent contains 12 ounces/gallon of water of CuSO4.5H2O, 10% by volume of concentrated sulfuric acid, 50 ppm of chloride ion from hydrochloric acid, and TECHNI-COPPER(copyright) W additive at 0.4% by volume provided by Technic, Inc. of Providence, RI. The plating glasses were selectively deposited through an inert mask.
The electroplated copper that is presently being used as line and via level interconnections in semiconductor devices suffers from an initially high resistance which requires either a long time, i.e., three days, room temperature anneal or some shorter time elevated temperature anneal to reduce the films to acceptable resistance levels. Typically, electroplated copper films are deposited in a fine grained condition from baths that contain additives or dopants. With time, these initially small copper grains, i.e., in the range of approximately 20 nm, grow to a final large grain, i.e., in the range of 1,000 nm low stress microstructure during which time a resistance drop of approximately 20xcx9c30% occurs. The large grained, low resistance, plated copper is preferred since it has both better electromigration stress voiding behavior than fine grained copper films and the desired high electrical conductivity.
The plated copper films that are presently used in semiconductor devices as line and via level interconnections suffer from an initially high resistance which requires either a long time period, i.e., three days room temperature anneal or shorter time at elevated temperatures, to reduce the high resistance to acceptable resistance levels. The long anneal times required therefore places unacceptable limits on the fabrication process which results in a more expensive copper process. In order to speed up the fabrication processes, it is important that this grain growth and associated resistance drop, i.e., the resistance transient, occur in as short a time as possible.
It is therefore an object of the present invention to provide a method for plating copper conductors on an electronic substrate that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for plating copper conductors on an electronic substrate which produces copper films with short resistance transient.
It is a further object of the present invention to provide a method for plating copper conductors on an electronic substrate by carrying out the electroplating process in a plating bath maintained at a temperature below 18xc2x0 C.
It is another further object of the present invention to provide a method for plating copper conductors on an electronic substrate wherein copper films of large grain size and low electrical resistance are plated.
It is still another object of the present invention to provide a method for plating copper conductors on an electronic substrate wherein copper films of low resistance transient are plated in a bath maintained at a low temperature and a low additive concentration of not more than 5 mL/L.
It is yet another object of the present invention to provide a method for plating copper conductors on an electronic substrate for producing copper films of short resistance transient wherein a low electrical resistance plated film can be obtained in less than 10 hours of room temperature annealing.
It is still another further object of the present invention to provide a method for plating copper conductors in a structure of high aspect ratio by a two-step plating process wherein two copper layers are separately plated.
It is yet another further object of the present invention to provide a method for plating copper conductors in a high aspect ratio via opening by plating a first layer of copper in a plating bath containing high additive concentration and then plating a second layer of copper in a plating bath containing low additive concentration such that a copper film of short resistance transient is obtained.
In accordance with the present invention, a method for plating copper conductors on an electronic substrate and devices formed are provided.
In a preferred embodiment, a method for plating copper conductors on an electronic substrate can be carried out by the operating steps of first providing an electroplating copper bath filled with an electroplating solution, maintaining the electroplating solution at a temperature between about 0xc2x0 C. and about 18xc2x0 C., and then electroplating a copper layer on the electronic substrate immersed in the electroplating solution.
In the method for plating copper conductors on an electronic substrate, the method may further include the step of maintaining the electroplating solution at a temperature preferably between about 5xc2x0 and about 15xc2x0 C., and more preferably between about 8xc2x0 C. and about 12xc2x0 C.
In an alternate embodiment, a method for plating copper conductors on an electronic substrate may be carried out by the operating steps of providing a copper electroplating solution in a plating bath, adding an additive to the copper electroplating solution to a concentration of not more than 5 mL/L, maintaining the copper electroplating solution at a temperature not higher than 18xc2x0 C. and electroplating a copper layer on the electronic substrate immersed in the copper electroplating solution.
In the method for plating copper conductors on an electronic substrate, the additive is added to the electroplating solution to a concentration of not more than 3 mL/L MLo, or to a concentration of not more than 15 mL/L MD. The method may further include the step of maintaining a wafer rotational speed at less than 100 RPM. The method may further include the step of maintaining a plating current density at least 15 mA/cm2. The method may further include the step of maintaining a deposition rate of at least 5 nm/sec. The method may further include the step of electroplating a copper layer to a thickness of at least 0.5 xcexcm.
The method for plating copper conductors on an electronic substrate may further include the steps of maintaining a additive concentration in the electroplating solution at not more than 5 mL/L, maintaining a wafer rotational speed at less than 100 RPM, maintaining a plating current density of at least 15 mA/cm2, and maintaining a deposition rate of at least 5 nm/sec.
In still another alternate embodiment, a method for plating copper conductors on an electronic substrate may be carried out by the operating steps of first depositing a first layer of copper on the electronic substrate in a first electroplating solution containing a additive concentration of more than 5 mL/L, and then depositing a second layer of copper on top of the first layer of copper in a second electroplating solution containing a additive concentration of less than 5 mL/L. The method may further include the step of plating a dual damascene structure of trench/via. The method may further include the step of depositing the first layer of copper in a via hole which has an aspect ratio of diameter/depth of at least ⅓.
The method for plating copper conductors in an electronic substrate by a dual-step plating method may further include the step of depositing the second layer of copper in a second electroplating solution maintained at a temperature not higher than 18xc2x0 C., the step of depositing the second layer of copper in a second electroplating solution with the substrate rotating at a rotational speed of less than 100 RPM, or the step of depositing the second layer of copper in a second electroplating solution that is maintained at a plating current density of at least 15 mA/cm2.
The method of plating copper conductors on an electronic substrate by a dual-step electroplating process may further include the step of depositing the second layer of copper in a second electroplating solution at a deposition rate of at least 5 nm/sec, or the step of depositing the second layer of copper in a second electroplating solution to a thickness of at least 0.5 xcexcm.
The method for plating copper conductors on an electronic substrate by a dual-step plating process may further include the steps of maintaining the second electroplating solution at a temperature of not higher than 18xc2x0 C., rotating the substrate at a speed of less than 100 RPM, conducting the plating at a current density of at least 15 mA/cm2, and depositing the copper layer at a deposition rate of at least 5 nm/sec.
The present invention is further directed to a semiconductor structure of a damascene or dual-damascene interconnect formed by a trench-filling process of electroplated Cu having an as-deposited grain size of not less than 0.05 xcexcm and a decrease in electrical resistance of at least 15% after a time period of not more than 30 hours at about 21xc2x0 C.
In the semiconductor structure of a damascene or dual-damascene interconnect, the as-deposited grain size of the electroplated Cu is between about 0.05 xcexcm and about 0.15 xcexcm. The grain size of the electroplated Cu after the time period of not more than 30 hours at about 21xc2x0 C. is between about 1.5 xcexcm and about 2 xcexcm.